Shrikanth Shirakol

Lecture 10 - HDL Programming using verilog: Simulations using xilinx by Shrikanth Shirakol 19:45
Lecture 10 - HDL Programming using verilog: Simulations using xilinx by Shrikanth Shirakol Shrikanth Shirakol 1,202 4 года назад
Lecture 17- HDL verilog: conditional statement (if-else) - D and T flip flop by Shrikanth Shirakol 9:56
Lecture 17- HDL verilog: conditional statement (if-else) - D and T flip flop by Shrikanth Shirakol Shrikanth Shirakol 646 4 года назад
Lecture 4 - HDL Programming using verilog: Dataflow modelling-3 by Shrikanth Shirakol 14:28
Lecture 4 - HDL Programming using verilog: Dataflow modelling-3 by Shrikanth Shirakol Shrikanth Shirakol 1,198 4 года назад
Lecture 3 - HDL Programming using verilog: Dataflow modelling-2 by Shrikanth Shirakol 14:56
Lecture 3 - HDL Programming using verilog: Dataflow modelling-2 by Shrikanth Shirakol Shrikanth Shirakol 1,699 4 года назад
Lecture 19- HDL verilog: conditional statement if-else - 4 bit up & down counter -Shrikanth Shirakol 12:38
Lecture 19- HDL verilog: conditional statement if-else - 4 bit up & down counter -Shrikanth Shirakol Shrikanth Shirakol 1,460 4 года назад
Inside The Office of Rs. 12,000 Crores Company | Ft. Srikant Velamakanni | KwK #67 55:12
Inside The Office of Rs. 12,000 Crores Company | Ft. Srikant Velamakanni | KwK #67 Kushal Lodha 44,782 1 год назад
55 - Dealing with Buttons in Verilog Debouncing & Edge Detection 43:51
55 - Dealing with Buttons in Verilog Debouncing & Edge Detection Anas Salah Eddin 6,680 3 года назад
Lecture 33 Verilog HDL: Traffic Signal/ Light Controller using state machine FSM -Shrikanth Shirakol 27:58
Lecture 33 Verilog HDL: Traffic Signal/ Light Controller using state machine FSM -Shrikanth Shirakol Shrikanth Shirakol 10,343 4 года назад
HDL Verilog: Online Lecture 23: Sequence Counter, Frequency/ Clock divider concept and analysis 49:47
HDL Verilog: Online Lecture 23: Sequence Counter, Frequency/ Clock divider concept and analysis Shrikanth Shirakol 5,222 3 года назад
State Machines - coding in Verilog with testbench and implementation on an FPGA 14:19
State Machines - coding in Verilog with testbench and implementation on an FPGA Visual Electric 42,863 3 года назад
HDL Verilog: Online Lecture 26: Sequential & Parallel blocks, fork and join, Named and Disable block 43:28
HDL Verilog: Online Lecture 26: Sequential & Parallel blocks, fork and join, Named and Disable block Shrikanth Shirakol 2,012 3 года назад
HDL Verilog: Online Lecture 33:Logic Synthesis,Extraction of Synthesis information from verilog code 41:51
HDL Verilog: Online Lecture 33:Logic Synthesis,Extraction of Synthesis information from verilog code Shrikanth Shirakol 2,989 3 года назад
Lecture 32 Verilog HDL: Sequential and parallel block (fork and join) by Shrikanth Shirakol 7:06
Lecture 32 Verilog HDL: Sequential and parallel block (fork and join) by Shrikanth Shirakol Shrikanth Shirakol 1,230 4 года назад
Verilog for Registers and Counters 25:05
Verilog for Registers and Counters Peter Mathys 48,458 9 лет назад
HDL Verilog: Online Lecture 5: Vectors, Integers, Real, Time, Arrays, Strings, Parameter, Memories 37:39
HDL Verilog: Online Lecture 5: Vectors, Integers, Real, Time, Arrays, Strings, Parameter, Memories Shrikanth Shirakol 1,205 3 года назад
Session-1: Crash Course on Pointers in C progrmming (Overview/Basics of C) by Shrikanth Shirakol 1:28:11
Session-1: Crash Course on Pointers in C progrmming (Overview/Basics of C) by Shrikanth Shirakol Shrikanth Shirakol 574 4 года назад
Lecture 5 - HDL Programming using verilog: Dataflow modelling-4 by Shrikanth Shirakol 8:33
Lecture 5 - HDL Programming using verilog: Dataflow modelling-4 by Shrikanth Shirakol Shrikanth Shirakol 1,155 4 года назад
HDL Verilog: Online Lecture 34: Logic Synthesis flow,Examples on extraction of synthesis information 45:40
HDL Verilog: Online Lecture 34: Logic Synthesis flow,Examples on extraction of synthesis information Shrikanth Shirakol 1,596 3 года назад
Lecture 6 - HDL Programming using verilog: Dataflow modelling-4 by Shrikanth Shirakol 15:11
Lecture 6 - HDL Programming using verilog: Dataflow modelling-4 by Shrikanth Shirakol Shrikanth Shirakol 1,793 4 года назад
Two hour event on "Career Guidance tips for programming" at SDMCET, Dharwad 1:53:47
Two hour event on "Career Guidance tips for programming" at SDMCET, Dharwad Shrikanth Shirakol 798 4 года назад
Lecture 2 - HDL Programming using verilog: Dataflow Modelling by Shrikanth Shirakol 18:25
Lecture 2 - HDL Programming using verilog: Dataflow Modelling by Shrikanth Shirakol Shrikanth Shirakol 2,894 4 года назад
Lecture 20: Solving Differential and Difference equations: Homogenous solution, Particular Solution 50:14
Lecture 20: Solving Differential and Difference equations: Homogenous solution, Particular Solution Shrikanth Shirakol 748 3 года назад
Lecture 28: Frequency Domain Analysis: Fourier Transform (FT) and Examples 45:55
Lecture 28: Frequency Domain Analysis: Fourier Transform (FT) and Examples Shrikanth Shirakol 472 3 года назад
Lecture 12- HDL verilog: Behavioral style Blocking and Nonblocking assignments by Shrikanth Shirakol 22:36
Lecture 12- HDL verilog: Behavioral style Blocking and Nonblocking assignments by Shrikanth Shirakol Shrikanth Shirakol 1,057 4 года назад
Lecture 22 HDL verilog: Frequency Divider (Clock Divider) -Shrikanth Shirakol 25:07
Lecture 22 HDL verilog: Frequency Divider (Clock Divider) -Shrikanth Shirakol Shrikanth Shirakol 9,825 4 года назад
Lecture 26- Verilog HDL- Design of SR, JK, T, D Flipflop using case statement in verilog 13:09
Lecture 26- Verilog HDL- Design of SR, JK, T, D Flipflop using case statement in verilog Shrikanth Shirakol 1,223 4 года назад

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