GATE CSE 2005 || Digital Electronics || GATE Insights Version: CSE

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MCQ (Single Correct Answer)
GATE CSE 2005
Consider the following circuit involving a positive edge triggered D FF.Consider the following timing diagram. Let Ai represent the logic level on the line A in the i-th clock period.Let A’ represent the complement of A. The correct output sequence on Y over the clock periods 1 through 5 is(A) A0 Al A1′ A3 A4(B) A0 Al A2′ A3 A4(C) Al A2 A2′ A3 A4(D) Al A2′ A3 A4 A5′

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