Комментарии:
No one can beat neso academy in terms of detailed explanation
ОтветитьYou making it simple...
ОтветитьSir, You are my life saviour! The word thanks is not enough to show my gratitude..
Ответитьthankyou dude
ОтветитьFor 4 bit down counter ...t flipflop use or j k flip flop??
ОтветитьEverything that is concievable is clearly stated. Geat job.
ОтветитьWas there a 4bit down counter diagram??
I didn't notice any, please provide timestamp.
Down counter’s wave form wrong , u have to take Qb on the bases of Qa’ and then u have to take Qb’ but u take Qb on bases of Qa . Am I right or wrong
Ответитьdon't we need to take preset for all flip flops in the second diagram? then only all the outputs would be high for first clock pulse right?
Ответитьwe can also use positive edge triggering
ОтветитьHello, how do I make it count down from 5 to 0?
ОтветитьCan i design asynchronous down counter by t flip flop ?
ОтветитьHey buddy. You are awesome man. Just splendid.I have completed a chapter from your Channel. I will be grateful to you vai.I am a Student of class Eleven. From Bangladesh 🇧🇩🇧🇩🇧🇩.
Love you😘😘
Teachers do not know how to teach
Teacher needs to take classes from neso man how to teach.
How did we get graph(rise/fall) for the last Qc?
ОтветитьIn the second circuit , set values of qa' qb' qc' as 1 initially and analyse qa qb qc accordingly .
Ответитьthx my doctor is fucking bitch
Ответитьegg thrower
ОтветитьI don't understand it can you explain it for the down counter for 4 bits?
Ответить❤🧡💛💚💙💜🤎🖤🤍
Ответитьjust awesome sir
ОтветитьWhere is 4 bit
Ответитьthx for the help
Ответитьthank you
ОтветитьLife saver before the exam ...
Ответитьfor the second config isnt it initially 000 ?
ОтветитьHow to pause and hold count
ОтветитьThank you !
ОтветитьThank you sir
ОтветитьI don't understand anything
Ответитьthanksssssssss GURUDEV
Ответитьi will contribute to you once i will start earning thankyou soomuch
ОтветитьThe best explanation i have got on counters so far
Ответитьthank you
Ответитьvekkama illaya da
ОтветитьThank You Sir
ОтветитьThank you so much sir 😊
ОтветитьI thought i was the only one confused at last but theres chaos in the comment😂😂😂😂 Plz someone help me to understand the last part
Ответитьcan we use T flipflop instead of jk to logic -1?
ОтветитьMan you are awesome
ОтветитьWhat will be the output if i take clock and output both as complemet (Qa,Qb,Qc)
ОтветитьAwesome lecture series ❤
ОтветитьShould have explained better man. Rarest disappointment from ur video
Ответитьawesome lecture, thank you!
Ответитьwhich circuit gives efficient design sir ?
ОтветитьSir the title was down counter but you drew the table for up counter I didn't get it
ОтветитьSir why u r not taking the initial values while calculating Qa,Qb, Qc for the 2nd ckt....pls solve this
ОтветитьTHANK YOU so much sir
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