JFET- Voltage Divider Bias Configuration Explained (with Solved Example)

Thank you

Can you tell me where you got the 3.3 mA and 8mA?

What happens if Vgs is positive?

How can we determine Q point for this configuration ?

Guys are athere any differences between Idq and Id or Vds and Vdsq or Vgs and Vgsq

Especially the parts where you simplify everything ☹️☹️😩😩😩😩😫😫

Sir I’m grateful for the video but can you please try not to skip so much of calculation stages please 🥺🥺🥺🥺it’s really stressful when you find the right video but the thing you want the most is what the tutor skips 😭😭😭😭😭😭 re do the ID current solution step by step please

Please help how to solve those large quadratics in jfet voltage divider problems

Bro, you have no idea just how thankful i am for this vid. Thanks

Can you please tell me how you reached from the second line to third line at 12.50 mins

Sir How to find Rs(min)

where is the subtitle

Great video sir 👍👌💚

thank you sir. can you tell me where does 1100 come from?

Very well explained !!
Can you also make videos on Feedback amplifiers?

Sir please review! the formula use in mathematical approach to make Q.Eq was wrong.

Bhiaya kya aap JFET k small signal analysis videos laa skte hain ? Bohut helpl ho jayegi

Thank you, this helped me

The capacitor is a delay timer

I waited for this video and it is released 2 weeks after my final exam😑

Rs = 550, Vds ≈ 4.75 V, Vgs ≈ -0.89 V, Id ≈ 5.5mA

Rs_min ~ 470 ohm (<= this is wrong, for more info pls see below)

Sir do a video on SCR

Excellent 👌 as usual 👍

Bro which department u studied in college bro please tell me

Best explanation 👌🏻👌🏻

Brother 1st view

Brother 1st view

Nice expilation