Debug an FPGA with a tiny interpreter -- Christopher Lozinski -- 2024-06-22

Many FPGAs have a hard or soft CPU (Risc-V, Arm, Nios, Microblaze)... is the idea that you communicate to this CPU in order to exercise some FPGA logic?

Any other tools that help in debugging Logic, without the tedious effort of manually creating testbenches? For example, Anything from SynaptiCAD, Active-HDL? Or thoughts on Amaranth-lang HDL (nMigen/Whitequark) vs Migen/LiteX (Enjoy-Digital)?