Writing Simulation Testbench on VHDL with VIVADO

Hello, great job! can you also show how to program the stimulus of a clock? this is what i was missing...

Thank you! That was great.

Thank you so much for the thorough explanation!

hi, can we simply add components and uut lines if we have multiple blocks to test? I am doing it but does not work. do you have any suggestion? it gives me error on the second component

i cant understand anything he says

Just Awful