Writing a Verilog Testbench

Writing a Verilog Testbench

aldecinc

7 лет назад

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@shreyashpatel9124
@shreyashpatel9124 - 12.11.2017 03:52

in test bench why datatype reg is used for input pins

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@sivakumar-lb5pk
@sivakumar-lb5pk - 25.06.2020 14:29

Which software tool you used here ?

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@bakeronews1
@bakeronews1 - 28.07.2020 06:21

How you got to the test bench???????????? Stop skipping steps!!!!!!

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@vasilisnikitaras
@vasilisnikitaras - 28.02.2021 23:28

Amazing!

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@BrianThomas
@BrianThomas - 18.03.2022 05:08

@aldecinc So, here's the thing. Great video by the way. I've been looking all over and yours ranks up there in how you explain what Verilog even is . I love electronics. What's your advice for someone like me who's struggling to understand what you're taking about in this video. I don't know C+ but I do understand Python.

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@muraliguptapenugonda9257
@muraliguptapenugonda9257 - 04.09.2022 12:37

Very helpful , could you please tell me in which tool you are doing it?

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