Do You Really Need Power Planes? Are you sure? | Eric Bogatin

can we get schematic or pcb layout of victim line board? as it is really difficult to understand

@Robert

Thank you all the video contents it is inspiring =]

I doubt that return path only applied to ground return but not power return.
Same voltage rail for the +V and -V is subjected to the same signal +V and -V.
So when the signal is -V aka 0V the return path is ground again? The field itself is defined as two potential with different.
No different no field line, so this means when -V the return field is +V and this means the power plane itself is the return path for -V case.
Correct me if this is determined wrongly.
From DDR3 experiment I cannot see this could introduce noise enough to fail @ > 1000MT/s.

What about sensitive nets that route over a power plane split, but with an adjacent ground plane. For example, here's a typical 6-layer stackup we have and the sensitive net routed on layer 3 (inner signal). If routing on external layers is not an option, would stitching capacitors be advised?

1 Signal/Power
2 Ground
3 Inner Signal
4 Power
5 Ground
6 Signal/Power

Great video again! I watched this right after the one you made with Richard Hartley. I see you asked Eric several times wether the voltage on the power plane matters, but he kept saying no. On the other hand, Richard told you that when using a power plane as a reference, voltage does matter and it has to be the same voltage of the signal that is routed on top of it. I think there is some confusion here. I agree with Eric when he says that the voltage level doesn't matter for the propagation of the signal but when the signal gets to its destination IC, the field will spread, as Richard said. And this is why you should never reference a signal to a power plane whose voltage is different from the voltage that generated the signal. What do you think?

Thanks for sharing the lesson! I found it very helpful and interesting. I do have a question, thoug. At the end of the video, where you show the example of routing the signal plane and having a reference ground plane at the bottom, do you not get problems with the copper extending during heat cycles? There is a huge difference in copper mass on each side of the pcb afterall.

IT'S LEGENDARY! 😀

Thankfully

Rubert, could you ask Eric if its ok to run S/G/S/G. If in the first two layer is ok to run signal/ground in parallel or orthoganal ??? What is best practice in that case. Keep up the good work and thank you!

Wonderful talk 🎉!

Plane layers are dirt cheap these days, so use them. I usually do six layer boards for analog right now. Why? Because it means I don't have to think even for a split second about power, ground and routing... there is just space through the roof. What's the cost of that? A couple bucks for a small board. Unless you are in a production environment absolutely nobody cares about that money.

Once i did some tests for a sensordesign where the old design was passive with coaxial cable and i wanted to power an amlifier near the sensor element. To stay with the old reception system, i decided a triaxial cable. The cables outside conductor was forced to be the metallics enclosure voltage, so i decided it to be gnd. I later then decoupled the outside gnd to hf cause of course it collects charge and so noise from the outside especially the gnd was "not allowed to" recepted from the sensor, without ferrite in series with litthe resistors and then a cap to V+. So the inner ring conductor on cable had to be the positive supply voltage. since the inner ring conductor is more near to the signal, it has high coupling to the signal on the wire. So the whole amplifier module and the sensor was not ac reference-coupled to gnd, but instead to V+. on the reception, it was then coupled to gnd. i used a lot capacitors for the coupling. I had a V+ plane instead of a gnd plane in the sensor. the signal was as never seen before and as i like to do, i tested all circumstances with a "high frequency massage device" from "esoteric" store, to emmit outside noise to test for the best emc circumstances. Later then, i changed the dc level on the signalwire (signal only of ac interest) to the suply level, sourrounding it. This then lead to no more recognizeable "microphonic effect" anymore. of course the sensor now has a little metallic enclosure, on ac- decoupled gnd from the systems perspective, so something which can lead to an "antifaradayic cage", so i believe. So i routed the signal always nearest to V+ and away from enclosure. I learned a lot during the project, parallel watching your great videos!

thank you very much for very interesting video.

Fantastic video! If you read a book on EMC your idea about PCB design will change dramatically. Grounding is an important and less understood and often overlooked concept of PCB design. As a rule of thumb remember that for a PCB especially clocked digital(over 100KHz) ones, proper grounding is a must and you need to think of it right from the beginning! Either you need a ground plane or at least the old-fashioned ground grid.

I'm not sure if this was answered in the video (I couldn't find the answer): assuming you have two ground plans (SGGS), I see how return vias are needed to reduce noise for signal traces, but what about power traces? I suppose that return vias for power traces are either less important or not important. Is this correct? Edit: I asked ChatGPT, here's what it said (not sure if it's accurate)...

"It is generally recommended to use return vias for power traces as well when switching between layers on a 4-layer PCB. The purpose of a return via is to provide a low impedance return path for the signal or power trace, which helps to reduce electromagnetic interference (EMI) and noise.

When a signal or power trace is switched from one layer to another, it can create a discontinuity in the return path, which can result in high impedance and unwanted noise. By using a return via, the return path is maintained and the impedance is reduced, which can improve the signal integrity and reduce noise.

In addition, having a solid ground plane on layer 2 and 3 can also help to provide a low impedance return path for the power traces, which can further reduce noise and improve performance. It is important to carefully consider the layout of the PCB and the placement of the return vias to ensure proper grounding and signal integrity."

Really great video. I've seen a few now. I'm in the process of redesigning a couple of our PCBs. I'm going to try the 2 center ground plane strategy and see if it fixes a couple of minor issues.

The main question in my mind was if I need to use plane to distribute power from the voltage regulator and not if there should be a whole power plane in the stack of the PCB. This question remains unanswered.

I know about things like johson noise, but really is di/dt noise? I do not understand.

network processor running at 1000 A ? How come?

mils or mm

Hi Robert, could you have Dr. Bogatin on this power integrity with running simulation tool again?

This is a so-valuable video, thanks a lot Robert and Eric.

You can put an amp through 6 mil? Yes if you are bread boarding. How about an iphone selling a few hundred million per yr what is the reliability and at elevated temperature?

Following up on my previous comment, for the claim of 100mil trace for 10Amps, over 10cm length PCB we would need to design for 50 degree temperature rise and we would loose 1.8 watts on that trace. Am I missing something? Can someone corroborate the numbers?

I guess the main idea is to not use 10 degree C temp increase in your calculations. Playing with the digikey ipc2221 calculator, to get 6 mil trace (100mm long) for 1A in 1oz copper we must let the temperature rise be 30 degrees celsius for external layers. With that much small surface area I guess you wouldn't be able to feel any heat to touch.

i would be interested to see a 3rd comparison of the noise influence on the victim line when you put in decoupling capacitors on the 'no return vias' board

This changes my approach to power planes. Thank you.

This video was eye opening to me. Im designing USB powered board with 8bit atmel uC and i was worried about power distribution! Board contains only a uC, NE555 and couple of slow optocouplers and signals only a few milliAmps here and there. 😀 Your videos are one of the best contents on its on area. Greetings from Finlad!

Great Video!!!

Should we be adding return GND vias next to a power track via that is distributed from layer 1 to 4?
Assuming the following layer stack:
L1 signal and power
L2 GND
L3 GND
L4 signal and power

What about a 6 layer PCB of SGS SGS, where layer 1-3 and layer 4--6 are tightly coupled, with vias between 2 and 5?

What are you supposed to be connecting the stitching vias to if not to a copper ground pour on both sides? Should they just remain unconnected on the top layer?

Hello, can you show us how to make GND departures from signal paths 0.3mm and 1mm from power paths, on one board?!
Often when we designing AC circuits with high current, we use the same branch from the paths using Polygon Pour, a breakdown and short circuit can occur...
So it's really useful to know more about this program and this special option:)

It is said again and again that their should no GND pour on the outer layers. But all the layout datasheets I find for chip antenna or pcb antenna layouts show that ground pour. Is it because they just assume there is one, or do they really need them? I mean the GND plane is mostly part of the antenna.

What I didn’t understand at the end, if I have a solid ground plane on a 2-layer board, will a copper fill on the signal layer create problems or not? My understanding is that it’s better to have a copper fill and a solid ground plane with stitching vias because of the reduced inductance on the signal layer for decoupling capacitors and components and also smaller fields.

Thanks a lot for this video. I got a question, can copper pour on the PCB top layer be used to reduce EMC/EMI emission on a noisy chip (as a DC-DC buck converter)? Copper immediately under the chip should create a good return path and reduce emission, is it true?

Amazing video

A power plane eases the power distribution routing.

While this was a great video... there are a lot of questions that arise from this. Also, many of his examples seemed to be very specific and unique instances, rather than comparing his way vs generally accepted practices in the design field. For instance - who the hell has just a floating plane in the middle of their stack-up connected to nothing? Literally no one.... That power plane is connected to the ground plane through capacitors at just about every IC. His first example would have been significantly more enlightening if Eric had used a board configured like his, against a board with 2 ground planes connected through vias. In his last example, I wished he would have also had a 3rd example of micro board to test against. The exact same ones his students designed, but with also a ground flood on top layer around the signal traces. If having a ground flood on your signal layer does nothing (even with a ground plane directly under the signal layer).... SHOW THAT IN YOUR EXAMPLE. He's comparing apples to oranges here. Let's make it apples to apples, please

what i understood from the last couple of minutes in the video , it is not necessary to fill the top layer with copper pour and connect it to ground on bottom layer "in a double layer board" , this means we just do the majority of routing on the top layer and use only one solid continuous ground plan on the bottom layer , and that it is !

10 mils or 20 mils for 3A current, do we need to worry about dc drop ?

Where to get the power point?

Regarding copper pour. I used it because I was told it reduced waste in the PCB fabrication process (less copper sulfate perhaps).
I use a (mostly very) solid ground plane as signal return and try to cover any gaps in the ground plane with copper on another layer stitched with vias.

Give the current paths the smallest diameter circle in which to circulate and the current will take it which is a win for all.

My experience is with two layer PCBs and I make the bottom side ground and keep the routing to the top layer.

Use a capacitor to ground on EVERY signal that leaves the PCB right at the connectors to limit the bandwidth of the signals to no more than is necessary for the job at hand.

100 mil trace for 10A? Sure, if you can accept 65degC rise above ambient. Not sure this really makes sense is most practical applications.

I never get this much visualisation in my 12 years of industrial career
Its great interaction
Thanks lott Robert and great Eric sir

Eric i think you were misundersranding roberts question about the voltage of the power plane. I think he was ttying to say when referencing a power plane does referencing a power plane that doesnt power thr chip where the signal is coming or going vs referencing a power plane that does. Example being a pair of 3.3v chips but there signal is referencing a 5v plane vs a 3.3v plane. Since tge 5v plane doesnt have a DC connection to chips that genetated the sigbal wont that cause issues?