Introduction to FPGA Part 6 - Verilog Modules and Parameters | Digi-Key Electronics

[COUNT_WIDTH:0] is actually COUNT_WIDTH+1 bits wide, as 0 was included. This isn't terribly important in this case, as it just needs to be wide enough to hold MAX_COUNT and narrow enough to fit and satisfy timing; if you're lucky, the synthesizer might even tell that the top bit is constant and remove it.

Personally I prefer the #() syntax for setting parameters over defparam, e.g.:

clock_divider #(.COUNT_WIDTH(32), .MAX_COUNT(1500000-1)) div_1(.clk(clk), .rst(rst), .out(led[0]));

This avoids repeating the instance name and makes it easy to define multiple instances with the same parameters. Note that you don't have to match styles between the module definition and instantiation; they're parameters either way.

🔥🔥🔥🔥🔥

My compliments - I'm really enjoying this series. I haven't bought the hardware yet but I'm planning to quite soon. I think the pace and level of detail in this series is perfectly pitched - there is good initial information in here, and if the student wants to learn more, well... there's a whole internet to search for material. My compliments on a genuinely useful, concise series of videos.

Get a Zynq and combine your RTOS/embedded linux series with FPGA.

@Shawn Hymel HUGE thanks for the dark themed video, much easier on the old eyes ;-)

Thank ou for making this series. It is very helpful to get your concise take on using FPGA's. My question is are you going to do an episode describing how to use ICESTUDIO and/or GTK Wave?
I know you seem to be a windows guy, but many of us are linux users, and it would be very helpful to have some episodes addressing more free tools that we could use.

Although I already have a DE10-Standard board, I placed an order for an Ice Stick because of your tutorials.
Now all I'm missing is a breadboard with a bunch of buttons and LEDs, because this one doesn't come with much, but no complaints. Might get one of those cheap-generic "Arduino compatible" cases you generally see on Aliexpress \ Amazon and call it a day.
Would be nice to be able to show my friends what an FPGA is, beacuse I'm not taking my DE10 out of the dorms, lol.

In the world of programming languages one can take a module written in one language (e.g. GUI written in C++), a module written in another language (e.g. a numerical library written in Fortran) and under some circumstances link them into one executable. Is it possible in the world of HDLs? If yes, could you prepare a simple tutorial? I think it is a valid question as there are many open source cores written in different HDLs and one may want to "glue" e.g. a processor described in VHDL with a peripheral described in Verilog. Greetings from Poland.

Excellent series Shawn. Top drawer & nice and snappy. No waiting for slow typing and droning-on! Does mean I have to occasionally rewind 🤠.

Had an .apio issue with sample code for a couple of dev boards where the verilog in other module files was included in the top.v file using the ‘include metastatement. I’m assuming needed for some tool chains but apio is doing a sweep of all files in the folder to round up other modules instantiated elsewhere. So with the file include statement(s) you get an error from apio that the module is already declared.

Might help someone…. But apio is great & enjoying Verilog instead of my usual VHDL.

Muito Obrigado por democratizar esse conhecimento ❤

ICGOODFIND is a Chinese spot - distributor of electronic component chips. Contact us if needed.

It doesn't work if two outputs from the clock divider are connected to the same wire LED; Does it short in case the output signals are opposite?
Example:
led[0] = 0
led[1] = 1
That would be "short" I know it's lookup tables, but doesnt it make sense? Or is this somehow internally implemented as an OR gate?